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the sp5655 is a single chip frequency synthesiser designed for tv tuning systems. control data is entered in the standard i 2 c bus format. the device contains 2 addressable current limited outputs and 4 addressable bidirectional open-collector ports, one of which is a 3-bit adc. the information on these ports can be read via the i 2 c bus. the device has one fixed i 2 c bus address and 3 programmable addresses, programmed by applying a specific input voltage to one of the current limited outputs. this enables two or more synthesisers to be used in a system. features n complete 27ghz single chip system n high sensitivity rf inputs n programmable via i 2 c bus n low power consumption (5v, 30ma) n low radiation n phase lock detector n varactor drive amp disable n 6 controllable outputs, 4 bidirectional n 5-level adc n variable i 2 c bus address for multi-tuner applications n esd protection: 4kv, mil-std-883c, method 3015 (1) n switchable 4 512/1024 reference divider n pin and function compatible with sp5055s (2) (1) normal esd handling precautions should be observed. (2) the sp5055s does not have a switchable reference division ratio. sp5655 27ghz bidirectional i 2 c bus controlled synthesiser advance information supersedes july 1996 version, ds3743-4.3 ds3743 - 5.0 june 1998 fig. 1 pin connections C top view sp5655 1 2 3 4 5 6 7 8 mp16 16 15 14 13 12 11 10 9 charge pump crystal q1 crystal q2 sda scl ? i / o port p7 * i / o port p6 ? i / o port p5 drive output v ee rf input rf input v cc p0 output port i / o port p4 ? ? = logic level i/o port * = 3-bit adc input p3 output port/ add select applications n satellite tv n high if cable tuning systems thermal data u jc = 41 c/w u ja = 111 c/w ordering information sp5655 kg/mpas (tubes) sp5655s kg/mpad (tape and reel)
2 sp5655 electrical characteristics t amb = 2 20 c to 1 80 c, v cc = 1 45v to 1 55v, reference frequency = 4mhz. these characteristics are guaranteed by either production test or design. they apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. supply current prescaler input voltage prescaler input impedance prescaler input capacitance sda, scl input high voltage input low voltage input high current input low current leakage current sda output voltage charge pump current low charge pump current high charge pump output leakage current charge pump drive output current charge pump amplifier gain recommended crystal series resistance crystal oscillator drive level crystal oscillator negative resistance external reference input frequency external reference input amplitude output ports p0, p3 sink current p0, p3 leakage current p4-p7 sink current p4-p7 leakage current input ports p3 input current high p3 input current low p4, p5, p7 input voltage low p4, p5, p7 input voltage high p6 input current high p6 input current low typ. value conditions characteristic pin 12 13,14 13,14 13, 14 4,5 4,5 4,5 4,5 4,5 4 1 1 1 16 2 2 2 2 11, 10 11, 10 9-6 9-6 10 10 9,8,6 9,8,6 7 7 50 3 0 500 10 750 2 70 07 10 27 30 50 2 6 50 6 170 6400 80 1000 1 40 300 55 15 10 2 10 10 04 6 5 200 8 200 15 10 10 1 10 2 10 08 1 10 2 10 units min. max. ma mvrms w pf v v m a m a m a v m a m a na m a w mv p-p w mhz mvrms ma m a ma m a m a m a v v m a m a v cc = 45v to 55v (note 1) 120mhz to 27ghz sinewave, see fig. 5 input voltage = v cc input voltage = 0v when v cc = 0v sink current = 3ma byte 4, bit 2 = 0, pin 1 = 2v byte 4, bit 2 = 1, pin 1 = 2v byte 4, bit 4 = 1, pin 1 = 2v v pin 16 = 07v parallel resonant crystal (note 2) ac coupled sinewave ac coupled sinewave v out = 12v v out = 132v v out = 07v v out = 132v v pin 10 = v cc v pin 10 = 0v see table 3 for adc levels notes 1. maximum power consumption is 220mw with v cc = 55v and all ports off. 2. resistance specified is maximum under all conditions.
3 sp5655 supply voltage rf input voltage port voltage total port output current address select voltage rf input dc offset charge pump dc offset drive output dc offset crystal oscillator dc offset sda, scl input voltage storage temperature junction temperature parameter conditions port in off state port in on state port in on state 12 13,14 6-11 6-9 10, 11 6-9 10 13-14 1 16 2 4,5 pin absolute maximum ratings all voltages are referred to v ee and pin 3 at 0v max. min. units 7 25 14 6 14 50 v cc 1 03 v cc 1 03 v cc 1 03 v cc 1 03 v cc 1 03 6 1 150 1 150 value 2 03 2 03 2 03 2 03 2 03 2 03 2 03 2 03 2 03 2 03 2 55 v v p-p v v v ma v v v v v v c c fig. 2 block diagram rf in 15-bit programmable divider prescaler 4 16 power on det i 2 c bus transceiver address select level 3 ttl comp 3-bit adc por preamp scl sda 15-bit latch divide ratio 6-bit latch port info lock det phase comp f control data latches and control logic f l 4 13 14 5 4 charge pump f comp divider 4 512/1024 dn up cp to os drive/ varicap out charge pump q1 q2 crystal v cc v ee 16 15 1 3 2 osc 4 port output drivers 9876 p4 p5 p6 p7 f pd 10 p3 11 p0 2
4 sp5655 functional description the sp5655 is programmed from an i 2 c bus. data and clock are fed in on the sda and scl lines respectively, as defined by the i 2 c bus format. the synthesiser can either accept new data (write mode) or send data (read mode). the lsb of the address byte (r/w) sets the device into write mode if it is low and read mode if it is high. the tables in fig. 3 illustrate the format of the data. the device can be pro- grammed to respond to several addresses, which enables the use of more than one synthesiser in an i 2 c bus system. table 4 shows how the address is selected by applying a voltage to p3. when the device receives a correct address byte, it pulls the sda line low during the acknowledge period, and during following acknowledge periods after further data bytes are programmed. when the device is programmed into the read mode, the controller accepting the data must pull the sda line low during all status byte acknowledge periods to read an- other status byte. if the controller fails to pull the sda line low during this period, the device generates an internal stop condition, which inhibits further reading. write mode (frequency synthesis) when the device is in write mode bytes 2 and 3 select the synthesised frequency, while bytes 4 and 5 control the output port states, charge pump, reference divider ratio and various test modes. once the correct address is received and acknowledged, the first bit of the next byte determines whether that byte is interpreted as byte 2 or 4; a logic 0 for frequency information and a logic 1 for control and output port information. when byte 2 is received the device always expects byte 3 next. similarly, when byte 4 is received the device expects byte 5 next. additional data bytes can be entered without the need to readdress the device until an i 2 c stop condition is recog- nised. this allows a smooth frequency sweep for fine tuning or afc purposes. if the transmission of data is stopped mid-byte (for exam- ple, by another device on the bus) then the previously pro- grammed byte is maintained. frequency data from bytes 2 and 3 are stored in a 15-bit register and used to control the division ratio of the 15-bit programmable divider. this is preceded by a divide-by-16 prescaler and amplifier to give excellent sensitivity at the local oscillator input, see fig. 5. the input impedance is shown in fig. 7. the programmed frequency can be calculated by multiply- ing the programmed division ratio by 16 times the comparison frequency f comp . when frequency data is entered, the phase comparator, via a charge pump and varicap drive amplifier, adjusts the local oscillator control voltage until the output of the programmable divider is frequency and phased locked to the comparison frequency. the reference frequency may be generated by an external source capacitively coupled into pin 2, or provided by an on- chip crystal controlled oscillator. the comparison frequency f comp is derived from the reference frequency via the refer- ence divider. the reference divider division ratio is switchable from 512 to 1024, and is controlled by bit 7 of byte 4 (ts0); a logic 1 to 512, a logic 0 for 1024. the sp5655 differs from the sp5055 in this respect, only 512 being available on the sp5055. note that the comparison frequency is 78125khz when a 4mhz reference is used, and divide by 512 is selected. bit 2 of byte 4 of the programming data (cp) controls the current in the charge pump circuit, a logic 1 for 170 m a and a logic 0 for 50 m a, allowing compensation for the variable tuning slope of the tuner and also to enable fast channel changes over the full band. when the device is frequency locked, the charge pump current is internally set to 50 m a regardless of cp. bit 4 of byte 4 (t0) disables the charge pump when it is set to a logic 1. bit 8 of byte 4 (os) switches the charge pump drive amplifiers output off when it is set to a logic 1. bit 3 of byte 4 (t1) enables various test modes when set high. these modes are selected by bits 5, 6 and 7 of byte 4 (ts2, and ts1, ts0) as detailed in table 5. when t1 is set low, ts2 and ts1 are assigned a dont care condition, and ts0 selects the reference divider ratio as previously de- scribed. byte 5 programs the output ports p0 and p3 to p7; a logic 0 for a high impedance output and a logic 1 for low impedance (on). read mode when the device is in read mode the status byte read from the device on the sda line takes the form shown in table 2. bit 1 (por) is the power-on reset indicator and is set to a logic 1 if the v cc supply to the device has dropped below 3v (at 25?c), for example, when the device is initially turned on. the por is reset to 0 when the read sequence is terminated by a stop command. when por is set high (at low v cc ), the programmed information is lost and the output ports are all set to high impedance. bit 2 (fl) indicates whether the device is phase locked, a logic 1 is present if the device is locked, and a logic 0 if the device is unlocked. bits 3, 4 and 5 (i2, i1, i0) show the status of the i/o ports p7, p5 and p4 respectively. a logic 0 indicates a low level and a logic 1 a high level. if the ports are to be used as inputs they should be programmed to a high impedance state (logic 1). these inputs will then respond to data complying with ttl type voltage levels. bits 6, 7 and 8 (a2, a1, a0) combine to give the output of the 5-level adc. the adc can be used to feed afc informa- tion to the microprocessor from the if section of the receiver, as illustrated in the typical application circuit. application a typical application is shown in fig. 4. all input/output interface circuits are shown in fig. 6. the sp5655 is function and pin equivalent to the sp5055 device apart from the switchable reference divider, and has much lower power dissipation, im- proved rf sensitivity and better esd performance.
5 sp5655 table 1 write data format (msb transmitted first) byte 1 byte 2 byte 3 byte 4 byte 5 address programmable divider programmable divider charge pump and test bits i/o port control bits 1 2 14 2 6 cp p6 0 2 13 2 5 t1 p5 0 2 12 2 4 t0 p4 0 2 11 2 3 ts2 p3 ma0 2 9 2 1 ts0 x ma1 2 10 2 2 ts1 x a a a a a msb 1 0 2 7 1 p7 lsb 0 2 8 2 0 os p0 fig. 3 data formats a : acknowledge bit ma1, ma0 : variable address bits (see table 4) cp : charge pump current select t1 : test mode selection t0 : charge pump disable ts2, ts1, ts0 : operation mode control bits (see table 5) os : varactor drive output disable switch p7, p6, p5, p4, p3, p0 : control output port states por : power on reset indicator fl : phase lock detect flag i2, i1, i0 : digital information from ports p7, p5 and p4 respectively a2, a1, a0 : 5-level adc data from p6 (see table 3) x : dont care table 2 read data format 1 por 1 a0 byte 1 byte 2 address status byte 1 fl 0 i2 0 i1 0 i0 ma0 a1 ma1 a2 a a address select input voltage 0v to 02v cc always valid 03v cc to 07v cc 08v cc to 132v table 3 adc levels ma0 0 1 0 1 ma1 0 0 1 1 table 4 address selection voltage input to p6 06v cc to 132v 045v cc to 06v cc 03v cc to 045v cc 015v cc to 03v cc 0v to 015v cc a1 0 1 1 0 0 a2 1 0 0 0 0 a0 0 1 0 1 0 t1 0 0 1 1 1 1 1 ts2 x x 0 0 1 1 1 ts1 x x 0 1 0 0 1 ts0 0 1 x x 0 1 x operation mode description normal operation, test modes disabled, reference divider ratio = 1024 normal operation, test modes disabled, reference divider ratio = 512 charge pump source (down). status bit fl set to 0 charge pump sink (up). status bit fl set to 1 ports p4, p5, p6, p7set to state x port p7 = f pd /2; p4, p5, p6 set to state x port p7 = f pd ; p6 = f comp ; p4, p5 set to state x table 5 operation modes notes x = dont care for further details of test modes, see table 6
6 sp5655 fig. 4 typical application fig. 5 typical input sensitivity sp5655 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 39n 22k 180n 1n 1 5v 01 m bcw31 18p 4mhz crystal 1 5v i 2 c bus sda scl control micro 10n 10k 47k v t 1 30v 22k p3 if section afc out 1 12v if signal 1 12v 1n oscillator output varicap input satellite tuner p0 p4 p5 p6 p7 300 150 100 50 120 1000 2000 2700 3000 3500 frequency (mhz) v in (mv rms into 50 w ) operating window
7 sp5655 fig. 6 sp5655 input/output interface circuits v ref rf inputs 400 400 150 charge pump drive output scl / sda rf input loop amplifier ports p7-p4 scl and sda inputs reference oscillator ports p0-p3 3k ack * * on sda only crystal q1 crystal q2 os (o/p disable) 67k v cc v cc v cc port v cc 3k port 3k v cc port p3 only 12k
8 sp5655 fig. 7 typical input impedance, application notes an application note, an168, is available for designing with synthesisers such as the sp5655. it covers aspects such as loop filter design, decoupling and i 2 c bus radiation problems. the application note is published in the mitel semiconductor media ic handbook. a generic test/demonstration board has been produced, which can be used for the sp5655. a circuit diagram and layout for the board are shown in figs. 8 and 9. the board can be used for the following purposes: (a) measuring rf sensitivity perfomance (b) indicating port function (c) synthesising a voltage controlled oscillator (d)testing external reference sources the programming codes relevant to these tests are given in table 6. fig. 8 test board circuit 26ghz s 11: z o = 50 w normalised to 50 w frequency marker step = 500mhz j 2 j 1 j 0.5 j 0.2 0 2 j 0.2 2 j 0.5 2 j 1 2 j 2 1 0.5 0.2 j 5 2 j 5 2 5 sp5655 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1 5v r3 47k d3 r6 47k d6 r2 47k d2 r1 47k d1 r4 47k d4 r5 47k d5 1 5v 1 12v c10 1n r13 12k c4 1n r14 22k p4 678 91011 1 12v c11 1n pin no. c5 1n c3 47n r7 22k c2 220n tr1 2n3904 r9 10k r10 47k c14 10n p3 var gnd tr2 2n3906 c7 100n c8 100n c9 100n 1 5v 1 30v 1 12v p2 r8 22k c12 100p c13 100p p1 data/sda clock/scl enable/address sel c1 18p x1 4mhz external reference sk2 c6 10n (not fitted, see note) tp1 s2 s1 r11 3k r12 1k sk1 rf input note to use an external reference, capacitor c6 must be fitted and capacitor c1 removed from the board.
9 sp5655 top view (ground plane) notes 1. circuit schematic is shown in fig. 8 2. all suface mount components are mounted on underside of board fig. 9 test board layout tp1 = pin 3 dc bias underside (surface mounted components side)
10 sp5655 normal operation, reference divider ratio = 1024 normal operation, reference divider ratio = 512 charge pump source (down), fl set to 0 charge pump sink (up), fl set to 1 port p7 = f pd /2 port p7 = f pd , p6 = f comp charge pump disable, reference divider ratio = 512 varactor line disable, reference divider ratio = 512 charge pump and varactor line disable, reference divider ratio = 512 operation mode description table 5 operation modes hex code (byte 4) cp high mode cp low mode cc ce e2 e6 ea ee de cf df 8c 8e a2 a6 aa ae 9e 8f 9f test modes as explained in the functional description, the sp5655 can be programmed into a numb er of test modes. these are invoked by programming hex codes into byte 4, those most commonly used being shown in table 6. other codes will also apply due to dont care conditions, which are assumed to be 1 in the table. note: when looking at f pd or f comp signals from ports p7 and p6. byte should be sent twice, first to set the desired reference division ratio then to switch on the chosen test mode. the pulses can then be measured by simply connecting an oscilloscope or counter to the relevant output pin on the test board.

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